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AD7352 Datenblatt(PDF) 13 Page - Analog Devices

Teilenummer AD7352
Bauteilbeschribung  Differential Input,Dual,Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC
PDF  17 Pages
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
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AD7352 Datenblatt(HTML) 13 Page - Analog Devices

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Preliminary Technical Data
AD7357
Rev. PrD | Page 13 of 17
MODES OF OPERATION
The mode of operation of the AD7357 is selected by controlling
the (logic) state of the CS signal during a conversion. There are
three possible modes of operation: normal mode, partial power-
down mode and full power-down mode. After a conversion has
been initiated, the point at which CS is pulled high determines
which power-down mode, if any, the device enters. Similarly, if
already in a power-down mode, CS can control whether the
device returns to normal operation or remains in power-down.
These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for the
differing application requirements.
NORMAL MODE
This mode is intended for applications needing fastest
throughput rates since the user does not have to worry about
any power-up times with the AD7357 remaining fully powered
at all times. Figure 14 shows the general diagram of the
operation of the AD7357 in this mode.
SCLK
LEADING ZEROS + CONVERSION RESULT
CS
DOUTA
DOUTB
114
10
Figure 14. Normal Mode Operation
The conversion is initiated on the falling edge of CS, as
described in the Serial Interface section. To ensure that the part
remains fully powered up at all times, CS must remain low until
at least 10 SCLK falling edges have elapsed after the falling edge
of CS. If CS is brought high any time after the 10th SCLK falling
edge but before the 16th SCLK falling edge, the part remains
powered up, but the conversion is terminated and SDATAA and
SDATAB go back into three-state. 16 serial clock cycles are
required to complete the conversion and access the conversion
result for the AD7357. The SDATA lines do not return to three-
state after 16 SCLK cycles have elapsed, but instead do so when
CS is brought high again. If CS is left low for another 2 SCLK
cycles, two trailing zeros are clocked out after the data. If CS is
left low for a further 16 SCLK cycles, the result for the other
ADC on board is also accessed on the same SDATA line as
shown in Figure 20 (see the Serial Interface section).
Once 32 SCLK cycles have elapsed, the SDATA line returns to
three-state on the 32nd SCLK falling edge. If CS is brought high
prior to this, the SDATA line returns to three-state at that point.
Thus, CS may idle low after 32 SCLK cycles until it is brought
high again sometime prior to the next conversion if so desired,
since the bus still returns to three-state upon completion of the
dual result read.
Once a data transfer is complete and SDATAA and SDATAB have
returned to three-state, another conversion can be initiated after
the quiet time, tQUIET, has elapsed by bringing CS low again
(assuming the required acquisition time has been allowed).
PARTIAL POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7357 is in partial
power-down, all analog circuitry is powered down except for
the on-chip reference and reference buffers.
To enter partial power, the conversion process must be
interrupted by bringing CS high anywhere after the 2nd falling
edge of SCLK and before the 10th falling edge of SCLK, as
shown in Figure 15. Once CS has been brought high in this
window of SCLKs, the part enters partial power-down, the
conversion that was initiated by the falling edge of CS is
terminated, and SDATAA and SDATAB go back into three-state.
If CS is brought high before the 2nd SCLK falling edge, the part
remains in normal mode and does not power down. This avoids
accidental power-down due to glitches on the CS line.
SCLK
THREE-STATE
CS
DOUTA
DOUTB
114
10
2
Figure 15. Entering Partial Power-Down Mode
To exit this mode of operation and power up the AD7357 again,
a dummy conversion is performed. On the falling of CS, the
device begins to power up, and continues to power up as long as
CS is held low until after the falling edge of the 10th SCLK. The
device is fully powered up after approximately TBD μs has
elapsed, and valid data results from the next conversion, as
shown in Figure 16. If CS is brought high before the 2nd falling
edge of SCLK, the AD7357 again goes into partial power-down.
This avoids accidental power-up due to glitches on the CS line.
Although the device may begin to power up on the falling edge
of CS, it powers down again on the rising edge of CS. If the
AD7357 is already in partial power-down mode and CS is
brought high between the 2nd and 10th falling edges of SCLK, the
device enters full power-down mode.
FULL POWER-DOWN MODE
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes
substantially longer than that from a partial power-down. This



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