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SL811S/T
Document #: 38-08009 Rev. **
Page 19 of 27
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VDD1
3.3 VDC
SL811ST Device VDD Power.
16
IN
CLK/X1
12/48 MHz Clock or External Crystal X1 connection.
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OUT
X2
External Crystal X2 connection.
18
IN
nRST
SL811ST Device active low reset input.
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OUT
INTRQ
Active High Interrupt Request output to external controller.
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GND
GND
SL811ST Device Ground.
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BIDIR
D0
Data 0. Microprocessor Data/(Address) Bus.
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BIDIR
D1
Data 1. Microprocessor Data/(Address) Bus.
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BIDIR
D2
Data 2. Microprocessor Data/(Address) Bus.
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BIDIR
D3
Data 3. Microprocessor Data/(Address) Bus.
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GND
GND
SL811ST Device Ground.
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BIDIR
D4
Data 4. Microprocessor Data/(Address) Bus.
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BIDIR
D5
Data 5. Microprocessor Data/(Address) Bus.
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BIDIR
D6
Data 6. Microprocessor Data/(Address) Bus.
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BIDIR
D7
Data 7. Microprocessor Data/(Address) Bus.
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VDD1
3.3 VDC
SL811ST Device VDD Power.
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IN
A0
A0 = ’0’. Selects Addr. Pointer. Reg. Write Only. Note 1 A0 = ’1’. Selects Data
Buffer or Register.
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IN
nDACK
DMA Acknowledge. An active low input used to interface to an external DMA
controller.
44
OUT
nDRQ
DMA Request. An active low output used with an external DMA controller. nDRQ
and nDACK form the handshake for DMA data transfers.
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IN
nRD
Read Strobe Input. An active low input used with nCS to read registers/data
memory.
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Pin No.
Pin Type
Pin Name
Pin Description
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