Aug.2007

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WDT divider

TMRC (01H)

bit7

bit6

0

0

0

1

1

0

1

1

PB ports interrupt

PB6~0, in input mode, could be optioned as external interrupt source by setting PBINT (00H.2) = 1.

When the interrupt enabled and external signal changed from high to low, the PB port interrupt will take

into action and its interrupt vector is $3FF6H and $3FF7H.

A falling edge signal at PB ports will wake up CPU from HALT or STOP mode. When PB port interrupt is

enabled (PBINT=1), CPU will wake up from HALT or STOP mode, and serve PB port interrupt first and

then execute next instruction. If PB port interrupt is disabled, CPU will just be waked up and then

execute next instruction only. User should check which PB port the falling edge signal comes from by

PBF control register. If the falling edge is from PB0, the PBF.0 will be set to “1” by hardware. These flags

could be cleared by software.

Address

02H

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

NAME

PBF

#

PBF6

PBF5

PBF4

PBF3

PBF2

PBF1

PBF0

Read or Write

#

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Default Value

#

0

0

0

0

0

0

0

Timer0

ExCLK/PB3, which is listed in figure 4-3. User can preset timer0 counter by setting data into timer0

preload buffer T0BF(04H). The data read from T0BF(04H) will be the current count of timer0.

Timer0 will down count by every input clock when T0EN=1. When timer0 down count from 00H to FFH,

T0F will be set to “1” and if T0INT =1, the timer0 interrupt will occur. Timer0 will automatically reload data

from T0BF/04H (timer0 preset buffer). Therefore, user can preset timer0 new data into T0BF(04H)

before timer0 underflow and cause different interrupt time duties. That is, timer0 data will be loaded

from T0BF buffer after T0EN bit is set as “1” or timer0 underflows.

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