STA027 datasheet(28/44 Pages) STMICROELECTRONICS

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5 Register description

STA027

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CD00066274

Table 16.

5.7

SDI_CONFIGURATION registers description

5.7.1

POL_REQ :

Address : 0x59 (89)

Type : WO - DEC

Software Reset : 0

Description :

This register manage the polarity of the data REQ signal DREQ of the BS input interface.

If set to 0, data are requested when REQ = 0.

If set to 1, data are requested when REQ = 1.

5.7.2

INPUT_CONF :

Address : 0x5A (90)

Type : RW - DEC

Software Reset : 0

Description :

If set to 1 enable the configurability of the BSB input interfaces in burst mode thanks to following

Note that this embedded default configuration can be retrieved by user thanks to following

setting :

–

I_AUDIO_CONFIG1 = b00000000;// polarity choice

Bit fields

Comment

LR[4:0]

Position of the data within the LRCK phase :

- if CF1 = 0 (LSB), value must be set to[31 - SL[9:5] - bit position of the first bit

of data within the LRCK phase].

- if CF1 = 1 (MSB), value must be set to bit position of the first bit of data within

the LRCK phase.

Note:

that range of value for this bit position is [0:31].

LR[9:5]

Length-1 of the data.

Max value is 31.

LR[15:10]

Reserved : to be set to 0

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