PDSP16318/13618A

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Supersedes version in December 1993 Digital Video & DSP IC Handbook, HB3923-1

DS3708 - 2.4 September 1996

PDSP16318/PDSP16318A

Complex Accumulator

Advance Information

Fig. 2 PDSP16318 simplified block diagram

The PDSP16318 contains two independent 20-bit Adder/

Subtractors combined with accumulator registers and shift

structures. The four port architecture permits full 20MHz

throughout in FFT and filter applications.

Two PDSP16318As combined with a single PDSP16112A

Complex Multiplier provide a complete arithmetic solution for

a Radix 2 DIT FFT Butterfly. A new complex Butterfly result

can be generated every 50ns allowing 1K complex FFTs to be

executed in 256µs.

FEATURES

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Full 20MHz Throughout in FFT Applications

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Four Independent 16-bit I/O Ports

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20-bit Addition or Accumulation

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Fully Compatible with PDSP16112 Complex Multiplier

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On Chip Shift Structures for Result Scaling

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Overflow Detection

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Independent Three-State Outputs and Clock

Enables for 2 Port 20MHz Operation

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1.4 micron CMOS

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500mW Maximum Power Dissipation

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84 Pin PGA or QFP packages

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K

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PIN 1A INDEX MARK

ON TOP SURFACE

AC84

Fig.1 Pin connections - bottom view (AC84 - PGA)

APPLICATIONS

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High speed Complex FFT or DFTs

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Complex Finite Impulse Response (FIR) Filtering

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Complex Conjugation

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Complex Correlation/Convolution

ASSOCIATED PRODUCTS

PDSP16112 16 x 12 Complex Multiplier

PDSP16116 16 x 16 Complex Multiplier

PDSP1601

ALU and Barrel Shifter

PDSP16330 Pythagoras Processor