ST7FOXK2 datasheet(90/226 Pages) STMICROELECTRONICS

90 / 226 page

On-chip peripherals

ST7FOXF1, ST7FOXK1, ST7FOXK2

90/226

Figure 43.

Block diagram of output compare mode (single timer)

Input capture mode

The 12-bit ATICR register is used to latch the value of the 12-bit free running upcounter

CNTR1 after a rising or falling edge is detected on the ATIC pin. When an Input Capture

occurs, the ICF bit is set and the ATICR register contains the value of the free running

upcounter. An IC interrupt is generated if the ICIE bit is set. The ICF bit is reset by reading

the ATICRH/ATICRL register when the ICF bit is set. The ATICR is a read only register and

always contains the free running upcounter value which corresponds to the most recent

Input Capture. Any further Input Capture is inhibited while the ICF bit is set.

Figure 44.

Block diagram of input capture mode

DCRx

OUTPUT COMPARE CIRCUIT

COUNTER 1

(ATCSR)

CMPIE

PRELOAD DUTY CYCLE REG0/1/2/3

ACTIVE DUTY CYCLE REGx

CNTR1

TRAN1

(ATCSR2)

OVF

(ATCSR)

CMPFx (PWMxCSR)

CMP

REQUEST

INTERRUPT

ATCSR

CK0

CK1

ICIE

ICF

12-BIT AUTORELOAD REGISTER

12-BIT UPCOUNTER1

fCPU

ATIC

12-BIT INPUT CAPTURE REGISTER

IC INTERRUPT

REQUEST

ATR1

ATICR

CNTR1

(1 ms

fLTIMER

@ 8MHz)

timebase

OFF

ST7FOXK2 Datenblatt(PDF) 90 Page - STMicroelectronics

ST7FOXK2 Datenblatt(HTML) 90 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL