MAX797CSLASHD datasheet(21/32 Pages) MAXIM

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Step-Down Controllers with

Synchronous Rectifier for CPU Power

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These equations are “worst-case” with 45 degrees of

phase margin to ensure jitter-free fixed-frequency opera-

tion and provide a nicely damped output response for

zero to full-load step changes. Some cost-conscious

designers may wish to bend these rules by using less

expensive (lower quality) capacitors, particularly if the

load lacks large step changes. This practice is tolerable,

provided that some bench testing over temperature is

done to verify acceptable noise and transient response.

There is no well-defined boundary between stable and

unstable operation. As phase margin is reduced, the

first symptom is a bit of timing jitter, which shows up as

blurred edges in the switching waveforms where the

scope won’t quite sync up. Technically speaking, this

(usually) harmless jitter is unstable operation, since the

switching frequency is now non-constant. As the

capacitor quality is reduced, the jitter becomes more

pronounced and the load-transient output voltage

waveform starts looking ragged at the edges.

Eventually, the load-transient waveform has enough

ringing on it that the peak noise levels exceed the

allowable output voltage tolerance. Note that even with

zero phase margin and gross instability present, the

output voltage noise never gets much worse than IPEAK

x RESR (under constant loads, at least).

Designers of RF communicators or other noise-sensi-

tive analog equipment should be conservative and

stick to the guidelines. Designers of notebook comput-

ers and similar commercial-temperature-range digital

systems can multiply the RESR value by a factor of 1.5

without hurting stability or transient response.

The output voltage ripple is usually dominated by the

ESR of the filter capacitor and can be approximated as

IRIPPLE x RESR. There is also a capacitive term, so the

full equation for ripple in the continuous mode is

VNOISE(p-p) = IRIPPLE x (RESR + 1 / (2 x pi x f x CF)). In

idle mode, the inductor current becomes discontinuous

with high peaks and widely spaced pulses, so the

noise can actually be higher at light load compared to

full load. In idle mode, the output ripple can be calcu-

lated as:

0.02 x RESR

VNOISE(p-p) = —————— +

RSENSE

0.0003 x L x [1 / VOUT + 1 / (VIN - VOUT)]

———————————————————

(RSENSE)2 x CF

Transformer Design

(MAX796/MAX799 Only)

Buck-plus-flyback applications, sometimes called “cou-

pled-inductor” topologies, need a transformer in order to

generate multiple output voltages. The basic electrical

design is a simple task of calculating turns ratios and

adding the power delivered to the secondary in order to

calculate the current-sense resistor and primary induc-

tance. However, extremes of low input-output differen-

tials, widely different output loading levels, and high turns

ratios can complicate the design due to parasitic trans-

former parameters such as inter-winding capacitance,

secondary resistance, and leakage inductance. For

examples of what is possible with real-world transformers,

see the graphs of Maximum Secondary Current vs. Input

Voltage in the Typical Operating Characteristics.

Power from the main and secondary outputs is lumped

together to obtain an equivalent current referred to the

main output voltage (see Inductor L1 for definitions of

parameters). Set the value of the current-sense resistor

at 80mV / ITOTAL.

PTOTAL = the sum of the output power from all outputs

ITOTAL = PTOTAL / VOUT = the equivalent output cur-

rent referred to VOUT

VOUT (VIN(MAX) - VOUT)

L(primary) = —————————————

VIN(MAX) x f x ITOTAL x LIR

VSEC + VFWD

Turns Ratio N = ——————————————

VOUT(MIN) + VRECT + VSENSE

where: VSEC is the minimum required rectified sec-

ondary-output voltage

VFWD is the forward drop across the secondary

rectifier

VOUT(MIN) is the minimum value of the main

output voltage (from the Electrical

Characteristics)

VRECT is the on-state voltage drop across the

synchronous-rectifier MOSFET

VSENSE is the voltage drop across the sense

resistor

In positive-output (MAX796) applications, the trans-

former secondary return is often referred to the main

output voltage rather than to ground in order to reduce

the needed turns ratio. In this case, the main output

voltage must first be subtracted from the secondary

voltage to obtain VSEC.

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