EM78F651NAPSSLASHNAPJ datasheet(13/58 Pages) EMC

13 / 58 page

EM78F651N

8-Bit Microcontroller

Product Specification (V1.1) 10.20.2006

• 9

(This specification is subject to change without further notice)

6.1.4 R3 (Status Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GP2

GP1

GP0

Bits 7 ~ 5 (GP2 ~ 0): General-purpose read/write bits

Bit 4 (T): Time-out bit

Set to 1 with the "SLEP" and "WDTC" commands, or during power up and

reset to 0 by WDT time-out.

Bit 3 (P): Power down bit

Set to 1 during power on or by a "WDTC" command and reset to 0 by a

"SLEP" command.

Bit 2 (Z): Zero flag

Set to "1" if the result of an arithmetic or logic operation is zero.

Bit 1 (DC): Auxiliary carry flag

Bit 0 (C): Carry flag

6.1.5 R4 (RAM Select Register)

Bit 7:

not used (read only). Bit 7 is always set to “0” at all time.

Bit 6

is used to select Bank 0 or Bank 1.

Bits 5~0 are used to select registers (address: 00~3F) in indirect addressing

mode.

Z flag of R3 is set to “1” when R4 content is equal to “3F.” When R4=R4+1, R4

content will select as R0.

See the configuration of the data memory in Fig 6-2.

6.1.6 R5 ~ R7 (Port 5 ~ Port 7)

R5 and R6 are I/O registers.

Only Bits 4, 5 of R5 are available (EM78F651NA)

Only Bits 0, 1, 4, 5 of R5 are available (EM78F651NB)

Only the lower 6 bits of R5 are available (EM78F651NC, D)

Only Bit 0 of R7 is available

6.1.7 R8 ~ R9

Reserved registers

EM78F651NAPS/NAPJ Datenblatt(PDF) 13 Page - ELAN Microelectronics Corp

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