MB95110M_07 datasheet(39/76 Pages) FUJITSU

39 / 76 page

MB95110M Series

(2) Source Clock/Machine Clock

(Vcc

= 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)

*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This

source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it

becomes the machine clock. Further, the source clock can be selected as follows.

• Main clock divided by 2

• PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)

• Sub clock divided by 2

• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)

*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.

• Source clock (no division)

• Source clock divided by 4

• Source clock divided by 8

• Source clock divided by 16

Parameter

Sym-

bol

Condi-

tions

Value

Unit

Remarks

Min

Typ

Max

Source clock

cycle time*1

(Clock before

setting division)

tSCLK

⎯

61.5

⎯

2000

When using main clock

Min : FCH

= 8.125 MHz, PLL multiplied by 2

Max : FCH

= 1 MHz, divided by 2

7.6

⎯

61.0

μs

When using sub clock

Min : FCL

= 32 kHz, PLL multiplied by 4

Max : FCL

= 32 kHz, divided by 2

Source clock

frequency

FSP

0.50

⎯

16.25

MHz When using main clock

FSPL

16.384

⎯

131.072

kHz

When using sub clock

Machine clock

cycle time*2

(Minimum

instruction

execution time)

tMCLK

61.5

⎯

32000

When using main clock

Min : FSP

= 16.25 MHz, no division

Max : FSP

= 0.5 MHz, divided by 16

7.6

⎯

976.5

μs

When using sub clock

Min : FSPL

= 131 kHz, no division

Max : FSPL

= 16 kHz, divided by 16

Machine clock

frequency

FMP

0.031

⎯

16.250

MHz When using main clock

FMPL

1.024

⎯

131.072

kHz

When using sub clock

FCH

(main oscillation)

FCL

(sub oscillation)

Devided by 2

Main PLL

× 1

× 2

× 2.5

× 4

Devided by 2

Sub PLL

× 2

× 3

× 4

SCLK

( source clock )

MCLK

( machine clock )

Clock mode select bit

( SYCC : SCS1, SCS0 )

Division

circuit

× 1

× 1/4

× 1/8

× 1/16

• Outline of clock generation block

MB95110M Datenblatt(PDF) 39 Page - fujitsu semiconductor

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