RA4L1 datasheet(98/125 Pages) RENESAS

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Table 2.64

Power-on reset circuit and voltage detection circuit characteristics (2) (2 of 2)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

Hysteresis width (LVD0, LVD1 and LVD2)

VLVH

—

LVD0 selected

—

Vdet1_0 to Vdet1_5 selected

—

Vdet1_6 to Vdet1_7 selected

—

Vdet1_8 to Vdet1_B selected

—

LVD2 selected

Note 1. When OFS1.LVDAS = 0.

Note 2. When OFS1.LVDAS = 1.

Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0,

Vdet1, and Vdet2 for the POR/LVD.

Internal reset signal

(active-low)

VCC

tVOFF

tPOR

tdet

VPOR

tdet

1.0 V

Figure 2.65

Voltage detection reset timing

Internal reset signal

(active-low)

VCC

tPOR

VPOR

1.0 V

tw(POR)

tdet

Note 1. tw(POR) is the time required for a power-on reset to be enabled while the external power VCC is being held below the

valid voltage (1.0 V).

When VCC turns on, maintain tw(POR) for 1.0 ms or more.

Figure 2.66

Power-on reset timing

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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