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RZ/G2LC Datenblatt(PDF) 14 Page - Renesas Technology Corp |
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RZ/G2LC Datenblatt(HTML) 14 Page - Renesas Technology Corp |
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14 / 74 page ![]() RZ/G2L Group, RZ/G2LC Group 1. Overview R01DS0484EJ0110 Rev.1.10 Page 14 of 74 May 30, 2025 1.2 Block Diagram The LSI internal bus of this LSI consists of the ACPU bus, MCPU bus, and system bus. Figure 1.1 shows the configuration of the buses. ACPU bus: A bus connected to Cortex-A55, DDR memory controllers, image processing units, and Storage and Network MCPU bus: A bus connected to Cortex-M33 and serial interface units System bus: A bus connected to the control registers of each unit |
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