9DB433

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

IDT®

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

6

9DB433

MAY 25, 2018

Electrical Characteristics–DIF_IN Clock Input Parameters

Electrical Characteristics–Current Consumption

Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics

TAMB=TCOM or TIND unless otherwise indicated, supply voltages per normal operation conditions; see Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Input Crossover Voltage -

DIF_IN

VCROSS

Cross Over Voltage

150

375

900

mV

1

Input Swing - DIF_IN

VSWING

Differential value

300

mV

1

Input Slew Rate - DIF_IN

dv/dt

Measured differentially

0.6

8

V/ns

1,2

Input Leakage Current

IIN

VIN = VDD , VIN = GND

-5

5

uA

Input Duty Cycle

dtin

Measurement from differential waveform

45

55

%

1

Input Jitter - Cycle to Cycle

JDIFIn

Differential measurement

0

125

ps

1

1 Guaranteed by design and characterization, not 100% tested in production.

2 Slew rate measured through +/-75mV window centered around differential zero.

TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

Operating Supply Current

IDD3.3OP

All outputs active @100MHz, CL = Full load;

93

120

mA

1

IDD3.3PD

All diff pairs driven

30

40

mA

1

IDD3.3PDZ

All differential pairs tri-stated

3

6

mA

1

1Guaranteed by design and characterization, not 100% tested in production.

Powerdown Current

TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

-3dB point in High BW Mode (TIND)1.5

2.8

4.1

MHz

1

-3dB point in High BW Mode (TCOM)2

2.8

4

MHz

1

-3dB point in Low BW Mode

0.7

1.1

1.4

MHz

1

PLL Jitter Peaking

tJPEAK

Peak Pass band Gain

1.5

2

dB

1

Duty Cycle

tDC

Measured differentially, PLL Mode

45

49.2

55

%

1

Duty Cycle Distortion

tDCD

Measured differentially, Bypass Mode @100MHz

-2

-0.4

2

%

1,4

Bypass Mode, VT = 50% (TIND)

3500

4263

4900

ps

1

Bypass Mode, VT = 50% (TCOM)

3500

4115

4500

ps

1,5

tpdPLL

PLL Mode VT = 50%

-250

-45

250

ps

1

Skew, Output to Output

tsk3

VT = 50%

40.0

50/60

ps

1,5

PLL mode

21

50

ps

1,3

Additive

Jitter in Bypass Mode

3

10

ps

1,3

1Guaranteed by design and characterization, not 100% tested in production.

2 I

REF = VDD/(3xRR).

For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.

3 Measured from differential waveform

4 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.

5 First number is commercial temp, second number is industrial temp.

Jitter, Cycle to cycle

tjcyc-cyc

PLL Bandwidth

BW

Skew, Input to Output

tpdBYP