With IC disabled: if VUVP rises above VUVP_th, the REST counter is incremented, and when it reaches rest_eoc

(corresponding to tUVP_REST), the IC resumes switching. If during the count-up, VUVP falls below VUVP_th for some

time, the REST counter is decremented during that time and the IC re-enabling is delayed accordingly.

Figure 31. UVP timing

VUVP

REST counter

IDRAIN

rest_eoc

VUVP_th

VDD

IC re-enabled

IC disabled

normal operation

disabled with ultra-low consumption (Iq_DIS)

normal operation

tUVP_REST

Restart

delay

VCCon

VCSon

DEB counter

tUVP_DEB

< tUVP_DEB

deb_eoc

An input undervoltage protection can be easily realized connecting the rectified mains to UVP pin through a

voltage divider, as shown in Figure 32. Connection for input undervoltage protection/disable (isolated or non-

isolated topologies).

Figure 32. Connection for input undervoltage protection/disable (isolated or non-isolated topologies)

C1

Cs

GND

DRAIN

GND

VCC

UVP

COMP

CONTROL

FB

VIPER31

RH

DIN

RL

~ AC

OVP

CIN

from VAUX or VOUT

C2

R2

VIPER31

General description

DS13285 - Rev 6

page 20/39