ADMV4530 datasheet(49/64 Pages) AD

49 / 64 page

Data Sheet

ADMV4530

analog.com

Rev. C | 49 of 64

Table 32. Bit Descriptions for REG001E

Bits

Bit Name

Description

Reset

Recommended

Access

[7:4]

CP_CURRENT

Charge Pump Current.

0x0

2.1 mA: 0x5

R/W

0000: 0.35 mA.

4.2 mA: 0xB

0001: 0.70 mA.

0010: 1.05 mA.

0011: 1.40 mA.

0100: 1.75 mA.

0101: 2.10 mA.

0110: 2.45 mA.

0111: 2.80 mA.

1000: 3.15 mA.

1001: 3.50 mA.

1010: 3.85 mA.

1011: 4.20 mA.

1100: 4.55 mA.

1101: 4.90 mA.

1110: 5.25 mA.

1111: 5.60 mA.

PD_POL

Phase Detector Polarity.

0x0

0x1

R/W

0: negative (simulate unlock condition).

1: positive (nominal).

PLL_PD

PLL Power Down. Setting this bit to 1 powers down all internal PLL blocks. The VCO, doubler,

RF, and IF chains remain powered up. The registers do not lose their values. After bringing

the PLL out of power-down (setting to 0), a write to REG0010 is required to relock the loop.

0x0

R/W

0: power up.

1: power down.

RESERVED

Reserved.

0x0

R/W

CNTR_RESET

Counter Reset. Setting this bit to 1 holds the N counter and R counter in reset. No signals

enter the phase frequency detector.

0x0

R/W

0: normal operation.

1: counter reset.

Address: 0x01F, Reset: 0x00, Name: REG001F

Table 33. Bit Descriptions for REG001F

Bits

Bit Name

Description

Reset

Recommended

Access

[7:5]

RESERVED

Reserved.

0x0

[4:0]

R_WORD

5-Bit R Counter. Programming to 0x0, results in divide by 32.

0x0

≥0x1

R/W

Address: 0x020, Reset: 0x00, Name: REG0020

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