ADP150AUJZ-2.65-R7 datasheet(12/20 Pages) AD

12 / 20 page

Data Sheet

ADP150

APPLICATIONS INFORMATION

analog.com

Rev. E | 12 of 20

CAPACITOR SELECTION

Output Capacitor

The ADP150 is designed for operation with small, space-saving

ceramic capacitors but functions with most commonly used capaci-

tors as long as care is taken with regard to the effective series

resistance (ESR) value. The ESR of the output capacitor affects the

stability of the LDO control loop. A minimum of 1 µF capacitance

with an ESR of 1 Ω or less is recommended to ensure the stability

of the ADP150. The transient response to changes in load current

is also affected by output capacitance. Using a larger value of

output capacitance improves the transient response of the ADP150

to large changes in the load current. Figure 27 and Figure 28 show

the transient responses for output capacitance values of 1 µF and

4.7 µF, respectively.

Figure 27. Output Transient Response, COUT = 1 µF

Figure 28. Output Transient Response, COUT = 4.7 µF

Input Bypass Capacitor

Connecting a 1 µF capacitor from VIN to GND reduces the circuit

sensitivity to the PCB layout, especially when long input traces

or high source impedance is encountered. If greater than 1 µF

of output capacitance is required, increase the input capacitor to

match the output capacitor.

Input and Output Capacitor Properties

Any good quality ceramic capacitors can be used with the ADP150,

as long as they meet the minimum capacitance and maximum

ESR requirements. Ceramic capacitors are manufactured with a

variety of dielectrics, each with different behavior over temperature

and applied voltage. Capacitors must have a dielectric adequate to

ensure the minimum capacitance over the necessary temperature

range and dc bias conditions. X5R or X7R dielectrics with a voltage

rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics

are not recommended, due to their poor temperature and dc bias

characteristics.

Figure 29 depicts the capacitance vs. the voltage bias characteristic

of a 0402, 1 µF, 10 V, X5R capacitor. The voltage stability of a

capacitor is strongly influenced by the capacitor size and voltage

rating. In general, a capacitor in a larger package or higher voltage

rating exhibits better stability. The temperature variation of the X5R

dielectric is about ±15% over the −40°C to +85°C temperature

range and is not a function of package or voltage rating.

Figure 29. Capacitance vs. Voltage Bias Characteristic

Use Equation 1 to determine the worst-case capacitance, account-

ing for capacitor variation over temperature, component tolerance,

and voltage.

CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)

(1)

where:

CBIAS is the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO)

over −40°C to +85°C is assumed to be 15% for an X5R dielectric.

The tolerance of the capacitor (TOL) is assumed to be 10%, and

the CBIAS is 0.94 µF at 1.8 V, as shown in Figure 29.

Substituting these values in Equation 1 yields

ADP150AUJZ-2.65-R7 Datenblatt(PDF) 12 Page - Analog Devices

ADP150AUJZ-2.65-R7 Datenblatt(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datenblatt Download

Link URL