74HC_HCT02

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2015. All rights reserved.

Product data sheet

Rev. 5 — 26 November 2015

2 of 15

NXP Semiconductors

74HC02; 74HCT02

Quad 2-input NOR gate

4.

Functional diagram

5.

Pinning information

5.1 Pinning

5.2 Pin description

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram (one gate)

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 4.

Pin configuration SO14 and (T)SSOP14

Fig 5.

Pin configuration DHVQFN14

Table 2.

Pin description

Symbol

Pin

Description

1Y to 4Y

1, 4, 10, 13

data output

1A to 4A

2, 5, 8, 11

data input

1B to 4B

3, 6, 9,12

data input

GND

7

ground (0 V)

VCC

14

supply voltage