74LVC2G34

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© NXP Semiconductors N.V. 2016. All rights reserved.

Product data sheet

Rev. 8 — 10 February 2016

2 of 18

NXP Semiconductors

74LVC2G34

Dual buffer gate

3.

Ordering information

4.

Marking

[1]

The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5.

Functional diagram

Table 1.

Ordering information

Type number

Package

Temperature range

Name

Description

Version

74LVC2G34GW

40 Cto +125 C

SC-88

plastic surface-mounted package; 6 leads

SOT363

74LVC2G34GV

40 Cto +125 C

TSOP6

plastic surface-mounted package (TSOP6); 6 leads

SOT457

74LVC2G34GM

40 Cto +125 C

XSON6

plastic extremely thin small outline package; no leads;

6 terminals; body 1

 1.45  0.5 mm

SOT886

74LVC2G34GF

40 C to +125 C

XSON6

plastic extremely thin small outline package; no leads;

6 terminals; body 1

 1  0.5 mm

SOT891

74LVC2G34GN

40 C to +125 C

XSON6

extremely thin small outline package; no leads;

6 terminals; body 0.9

 1.0  0.35 mm

SOT1115

74LVC2G34GS

40 C to +125 C

XSON6

extremely thin small outline package; no leads;

6 terminals; body 1.0

 1.0  0.35 mm

SOT1202

74LVC2G34GX

40 C to +125 C

X2SON6

plastic thermal extremely thin small outline package;

no leads; 6 terminals; body 1

 0.8  0.35 mm

SOT1255

Table 2.

Marking

Type number

Marking code[1]

74LVC2G34GW

YA

74LVC2G34GV

Y34

74LVC2G34GM

YA

74LVC2G34GF

YA

74LVC2G34GN

YA

74LVC2G34GS

YA

74LVC2G34GX

YA

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram (one gate)