Circuit Note

CN-0584

analog.com

Rev. 0 | 2 of 7

CIRCUIT DESCRIPTION

HARDWARE-IN-THE-LOOP

The CN0584 simplifies and accelerates the development and test

process for control systems using HIL emulation of expensive, com-

plex, or not-yet-developed hardware. Figure 2 shows a high-level

block diagram of a typical HIL setup using the CN0584 kit.

Figure 2. Hardware-in-the-Loop Simulation Setup

The electronic control unit (ECU) device under test (DUT) repre-

sents a controller, which produces digital output signals based

on analog feedback inputs from the device it is controlling. The

CN0584 emulates a device with custom hardware description lan-

guage (HDL) loaded into an FPGA board, providing a real-time

simulation of realistic performance.

One example of an HIL simulation that can be performed using the

CN0584 is emulating the load for a 3-phase motor controller. The

motor's behavior is first described in Simulink®, which is used to

generate an HDL module that can be integrated into the CN0584

HDL template.

Applying this example to Figure 2, the ECU produces pulse width

modulation (PWM) control signals, which are conditioned by three

channels on the analog front end board and digitized by the ADCs

on the data acquisition and signal generation board. Based on

these inputs, the HDL hardware model simulates parameters such

as the current draw, speed, inertia, and position of a modeled

motor. These parameters are converted to analog signals and

routed back to the ECU, which then closes the loop, adjusting its

output PWM signals based on this feedback.

The ECU can be quickly evaluated for nominal operating condi-

tions, corner cases (for example, maximum and minimum motor

load), and various failure modes, each of which can be quickly

implemented in simulation with no additional associated costs or

damage to physical hardware.

ANALOG MEASUREMENT AND SIGNAL

GENERATION

Input Voltage Range

The CN0584 supports an analog input voltage range of ±10 V by

default. Additional input ranges of ±5 V, ±4.096 V, ±2.5 V, and ±1.5

V are hardware-selectable.

Analog Input Protection

The CN0584 provides analog input protection on all four ADC and

DAC channels using the ADG5421F high voltage dual single-pole,

single-throw (SPST) switch, offering overvoltage protection up to

±60 V. This protection is particularly important for HIL applications

where high power signals may be present, and it also enables

users to quickly adapt or modify their setups without worrying about

miswiring or improper connections.

The ADG5421F is supplied by the +15 V and -15 V power rails, and

if either the S1 or S2 pin exceeds one of those voltage levels by

VT (0.7 V), the switch automatically turns off. For the ADCs, these

pins connect to the differential input ports; and for the DACs, they

connect to the two DAC channel output ports.

The ADG5421F also provides a fault flag (FF), which is routed to

the CN0585 and read by a MAX7301 serial peripheral interface

(SPI), 28-port I/O expander. The expander’s SPI port is routed

to the FMC connector, and read by the FPGA board. In normal

operation, the FF pin is pulled high. However, if an overvoltage

condition is detected, the FF pin is pulled low to indicate a fault has

occurred.

Output Voltage Range

The CN0584 supports an analog output voltage range of ±10

V by default. Additional output ranges of ±5 V, 0 V to +2.5 V,

0 V to +5 V, and 0 V to +10 V are hardware-selectable. Note

that the register settings, which are controlled using the provided

software interfaces, must also be updated for these output range

modifications to take effect.

SYSTEM PERFORMANCE

Latency

Figure 3 shows the test setup used to measure the latency of the

CN0584. A 1 MHz pulsed sine wave was generated from memory

using the FPGA and passed through to one DAC output channel.

This DAC output was monitored using an external scope and fed

back via subminiature version-A (SMA) cable as an input to one of

the ADC channels, where it was used as the input signal to the cor-

responding DAC channel. The output from this DAC channel was

measured using the same oscilloscope, enabling the measurement

of signal latency through the ADC input path, FPGA board, and

DAC output path.

Figure 3. Latency Test Setup

Figure 4 shows the latency and settling time of the CN0584 output

as captured by an oscilloscope. With the CN0584 DAC output set