ST10R167 datasheet(53/63 Pages) STMICROELECTRONICS

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ST10R167

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Notes 1. Guaranteed by design characterization.

2. RW-delay and tA refer to the next following bus cycle.

3. Read data is latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address

changes before the end of RD have no impact on read cycles.

t43

ALE falling edge to RdCS, WrCS

(no RW-delay)

-4 + tA

–-4 + tA

–ns

t46

RdCS to Valid Data In (with

RW-delay)

–16 + tC

–2TCL - 24 + tC

t47

RdCS to Valid Data In (no

RW-delay)

–36 + tC

–3TCL - 24 + tC

t48

RdCS, WrCS Low Time (with

RW-delay)

30 + tC

–

2TCL - 10 + tC

–ns

t49

RdCS, WrCS Low Time (no

RW-delay)

50 + tC

–

3TCL - 10 + tC

–ns

t50

Data valid to WrCS

26 + tC

–

2TCL - 14 + tC

–ns

t51

Data hold after RdCS

–

t53

Data float after RdCS (with

RW-delay)

–20 + tF

–

2TCL - 20 + tF

t68

Data float after RdCS (no RW-delay)

–

0 + tF

–TCL - 20 + tF

t55

Address hold after RdCS, WrCS

-10 + tF

–

-10 + tF

–ns

t57

Data hold after WrCS

6 + tF

–

TCL - 14 + tF

–ns

Table 19 : Demultiplexed bus characteristics (continued)

Symbol

Parameter

Max. CPU Clock

= 25MHz

Variable CPU Clock

1/2TCL = 1 to 25MHz

Unit

Min.

Max.

Min.

Max.

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