ST7263B datasheet(79/132 Pages) STMICROELECTRONICS

79 / 132 page

ST7263B

79/132

I²C BUS INTERFACE (Cont’d)

Figure 41. Transfer Sequencing

Legend:

S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge

EVx=Event (with interrupt if ITE=1)

EV1: EVF=1, ADSL=1, cleared by reading the SR1 register.

EV2: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register.

EV3: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register.

EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading the SR1 register. The BTF is cleared

by releasing the lines (STOP=1, STOP=0) or by writing the DR register (DR=FFh).

Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen.

EV4: EVF=1, STOPF=1, cleared by reading the SR2 register.

EV5: EVF=1, SB=1, cleared by reading the SR1 register followed by writing the DR register.

EV6: EVF=1, cleared by reading the SR1 register followed by writing the CR register

(for example PE=1).

EV7: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register.

EV8: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register.

Slave Receiver

Slave Transmitter

Master Receiver

Master Transmitter

S Address

Data1

Data2

.....

DataN

EV1

EV2

EV4

S Address

Data1

Data2

.....

DataN

EV1 EV3

EV3

EV3-1

EV4

Address

Data1

Data2

.....

DataN

EV5

EV6

EV7

Address

Data1

Data2

.....

DataN

EV5

EV6 EV8

EV8

ST7263B Datenblatt(PDF) 79 Page - STMicroelectronics

ST7263B Datenblatt(HTML) 79 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL