ST7SCR1E4 datasheet(46/102 Pages) STMICROELECTRONICS

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ST7SCR

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USB INTERFACE (Cont’d)

12.3.4 Register Description

INTERRUPT STATUS REGISTER (USBISTR)

Read/Write

Reset Value: 0000 0000 (00h)

These bits cannot be set by software. When an in-

terrupt occurs these bits are set by hardware. Soft-

ware must read them to determine the interrupt

type and clear them after servicing.

Note: The CTR bit (which is an OR of all the end-

point CTR flags) cannot be cleared directly, only

by clearing the CTR flags in the Endpoint regis-

ters.

Bit 7 = CTR

Correct Transfer.

This bit is set by hardware when a correct transfer

operation is performed. This bit is an OR of all

CTR flags (CTR0 in the EP0R register and

CTR_RX and CTR_TX in the EPnRXR and EP-

nTXR registers). By looking in the USBSR regis-

ter, the type of transfer can be determined from the

PID[1:0] bits for Endpoint 0. For the other End-

points, the Endpoint number on which the transfer

was made is identified by the EP[1:0] bits and the

type of transfer by the IN/OUT bit.

0: No Correct Transfer detected

1: Correct Transfer detected

Note: A transfer where the device sent a NAK or

STALL handshake is considered not correct (the

host only sends ACK handshakes). A transfer is

considered correct if there are no errors in the PID

and CRC fields, if the DATA0/DATA1 PID is sent

as expected, if there were no data overruns, bit

stuffing or framing errors.

Bit 6 = Reserved, forced by hardware to 0.

Bit 5 = SOVR Setup Overrun.

This bit is set by hardware when a correct Setup

transfer operation is performed while the software

is servicing an interrupt which occured on the

same Endpoint (CTR0 bit in the EP0R register is

still set when SETUP correct transfer occurs).

0: No SETUP overrun detected

1: SETUP overrun detected

When this event occurs, the USBSR register is not

updated because the only source of the SOVR

event is the SETUP token reception on the Control

Endpoint (EP0).

Bit 4 = ERR

Error.

This bit is set by hardware whenever one of the er-

rors listed below has occurred:

0: No error detected

1: Timeout, CRC, bit stuffing, nonstandard

framing or buffer overrun error detected

Note: Refer to the ERR[2:0] bits in the USBSR

Bit 3 = SUSP

Suspend mode request.

This bit is set by hardware when a constant idle

state is present on the bus line for more than 3 ms,

indicating a suspend mode request from the USB.

The suspend request check is active immediately

after each USB reset event and is disabled by

hardware when suspend mode is forced (FSUSP

bit in the USBCTLR register) until the end of

resume sequence.

Bit 2 = ESUSP

End Suspend mode.

This bit is set by hardware when, during suspend

mode, activity is detected that wakes the USB in-

terface up from suspend mode.

This interrupt is serviced by a specific vector, in or-

der to wake up the ST7 from HALT mode.

0: No End Suspend detected

1: End Suspend detected

Bit 1 = RESET

USB reset.

This bit is set by hardware when the USB reset se-

quence is detected on the bus.

0: No USB reset signal detected

1: USB reset signal detected

Note: The DADDR, EP0R, EP1RXR, EP1TXR,

EP2RXR and EP2TXR registers are reset by a

USB reset.

Bit 0 = SOF

Start of frame.

This bit is set by hardware when a SOF token is re-

ceived on the USB.

0: No SOF received

1: SOF received

Note: To avoid spurious clearing of some bits, it is

recommended to clear them using a load instruc-

tion where all bits which must not be altered are

set, and all bits to be cleared are reset. Avoid read-

modify-write instructions like AND, XOR...

CTR

SOVR ERROR SUSP ESUSP RESET SOF

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