STA015 datasheet(31/44 Pages) STMICROELECTRONICS

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ANCILLARY DATA BUFFER

Address: 0x7E - 0xB5 (126 - 181)

Type: RO

Software Reset: 0x00

Hardware Reset: 0x00

STA015 can extract max 56 bytes/MPEG frame.

To know the number of A.D. bits available every

MPEG frame, the ANCCOUNT_L and ANC-

COUNT_H registers (0x41 and 0x42) have to be

read.

The buffer dimension is 5 bytes, written by

STA015 core in sequential order. So the whole

set of ancillary data may be accessed in one

shot. The timing information to read the buffer

can be obtained by reading the FRAME_CNT

registers (0x67 - 0x69).

ISR

Address: 0xB6 (182)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

XXXXX

X = don’t care;

0 = no ancillary data

1 = Ancillary Data Available

The ISR is used by the microcontroller to under-

stand when a new ancillary data block is avail-

able.

ADPCM_CONFIG

Address: 0xB8 (184)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

AA1 AA0 ASM_EN AFM_EN

This register controls ADPCM engine and how

data must be compressed.

AFM_EN

ADPCM Frame Mode Enable

0 =

no frames (raw formed)

1 =

select the framed output formate for

ADPCM encoded data

ASM_EN: ADPCM Stereo Mode Enable

0 =

Disable stereo mode

1 =

Enable stereo mode

AA0,AA1:

ADPCM Algorithm selection

The ADPCM encoding/decoding algorithm

can be selected according to the following

table:

AA1

AA0

DVI algorithm

G723-24 algorithm (24kbp/s)

G721 algorithm (32kbp/s)

G723-40 algorithm (40kbp/s)

GPSO_ENABLE

Address: 0xB9 (185)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

XXXXXXX

GEN

This register enable/disable the GPSO interface.

Setting the GEN bit will enable the serial interface

for ADPCM data retrieving. Reset GEN bit to dis-

able GPSO interface.

STA015-STA015B-STA015T

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