V61C3181024 datasheet(2/10 Pages) MOSEL

2 / 10 page

V61C3181024 Rev. 1.3 February 1999

MOSEL VITELIC

V61C3181024

Pin Descriptions

A0–A16

Address Inputs

These 17 address inputs select one of the 128K x 8

bit segments in the RAM.

CE1, CE2 Chip Enable Inputs

CE1 is active LOW and CE2 is active HIGH. Both

chip enables must be active to read from or write to

the device. If either chip enable is not active, the

device is deselected and is in a standby power

mode. The I/O pins will be in the high-impedance

state when deselected.

Output Enable Input

The Output Enable input is active LOW. When OE

is LOW with CE LOW and WE HIGH, data of the

selected memory location will be available on the

I/O pins. When OE is HIGH, the I/O pins will be in

the high impedance state.

Write Enable Input

An active LOW input, WE input controls read and

write operations. When CE and WE inputs are both

LOW, the data present on the I/O pins will be

written into the selected memory location.

I/O0–I/O7 Data Input and Data Output Ports

These 8 bidirectional ports are used to read data

from and write data into the RAM.

VCC

Power Supply

GND

Ground

Pin Configurations (Top View)

32-Pin SOJ

32-Pin TSOP-I

3181024 02

A10

I/O0

I/O1

I/O2

GND

A11

CE2

A12

A13

A14

A15

A16

CE1

I/O7

I/O6

I/O5

I/O4

I/O3

VCC

3181024 03

A15

A14

A13

A12

A11

VCC

A10

A16

CE2

I/O6

I/O7

I/O5

I/O4

I/O3

I/O1

I/O2

VSS

CE1

I/O0

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