V61C51161024 datasheet(2/10 Pages) MOSEL

2 / 10 page

V61C51161024 Rev. 1.0 July 1998

MOSEL VITELIC

V61C51161024

Pin Descriptions

A0–A15

Address Inputs

These 16 address inputs select one of the 64K x 16

bit segments in the RAM.

Chip Enable Input

CE is active LOW. It must be active to read from or

write to the device. If chip enable is not active, the

device is deselected and is in a standby power

mode. The I/O pins will be in the high-impedance

state when deselected.

Output Enable Input

The output enable input is active LOW. When OE

is Low with CE Low and WE High, data will be pre-

sented on the I/O pins. The I/O pins will be in the

high impedance state when OE is High.

UBE, LEB

Byte Enable

Active low inputs. These inputs are used to enable

the upper or lower data byte.

Write Enable Input

The write enable input is active LOW and controls

read and write operations. With the chip enabled,

when WE is HIGH and OE is LOW, output data will

be present at the I/O pins; when WE is LOW and

OE is HIGH, the data present on the I/O pins will be

written into the selected memory locations.

I/O0–I/O15

Data Input and Data Output Ports

These 16 bidirectional ports are used to read data

from and write data into the RAM.

VCC

Power Supply

GND

Ground

Pin Configurations (Top View)

44-Pin SOJ

44-Pin TSOP-II (Standard)

144

6151161024-02

441

540

837

936

I/O0

I/O1

I/O2

I/O3

VCC

GND

I/O4

I/O5

I/O6

I/O7

UBE

LBE

I/O15

I/O14

I/O13

I/O12

VCC

GND

I/O11

I/O10

I/O9

I/O8

A15

A14

A13

A12

A10

A11

I/O0

I/O1

I/O2

I/O3

VCC

GND

I/O4

I/O5

I/O6

I/O7

A15

A14

A13

A12

UBE

LBE

I/O15

I/O14

I/O13

I/O12

GND

VCC

I/O11

I/O10

I/O9

I/O8

A10

A11

6151161024-03

V61C51161024 Datenblatt(PDF) 2 Page - Mosel Vitelic, Corp

V61C51161024 Datenblatt(HTML) 2 Page - Mosel Vitelic, Corp

Html Pages

1 2 3 4 5 6 7 8 9 10

Datenblatt Download

Link URL