STLC1502 datasheet(68/81 Pages) STMICROELECTRONICS

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STLC1502

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Figure 14: PCM-block Interconnection Scheme

The PCM interface has 5 main signals:

•

DR (output): this is the serial data stream that the PCM sends to the codec

•

DX (input): this is the serial data stream sent by the codec and received by the PCM block

•

PCLK (input/output): this is the PCM clock sent to codec. In the application, the frequency is

2.048Mhz. The PCM clock can be generated by the PCM block from internal Master clock or can be

input externally, according to the bit CLKEN in configuration register

•

PFS (input/output): this signal is asserted high when the frame number zero is present on the serial

data stream; it is possible to program the codec so that the PCM block asserts this signal on a given

frame (FS). The same frame number is always present in the same time on DR and DX. The PFS

can be generated by division from PCLK or can be input externally, according to FSEN in the config-

uration register.

10.1 Miscellaneous Interface

This interface has two signals:

•

RSTn (input): this is the hardware active low reset

•

CLK (input): this is the master input clock coming from the external oscillator at 2.048Mhz in the cur-

rent application.

10.2 Interrupt Event Management

There are two interrupt lines that goes to the D950.

•

ITR3 line (Overrun)

•

ITR7 line (Frame synch).

PCLK

PFS

XAE(15:0)

XDE(15:0)

XWREn

XRDEn

XBSEn

ITR3n

ITR7n

RSTn

CLK

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