STLC5464 datasheet(38/83 Pages) STMICROELECTRONICS

38 / 83 page

V - CLOCK TIMING

V.1 - Synchronization Signals delivered by the system

For one of three different input synchronizations which is programmed, FSCG and FSCV* signals

delivered by the

Multi-HDLC are in accordance with the figure hereafter.

t5h

t5l

Bit4

Bit5

Bit0

Bit1

Bit6

Bit7

Bit3

Time S lot 31

Time S lot 0

t4 CGI

CLOCK B

CLOCK A

1) S y Mode

F ra me A (or B)

2) G CI Mode

F ra me A (or B)

3) V* Mod e

F ra me A (or B)

DIN 0/8, ECHO

DO UT 0/7, CB

if FS = FSCG

TDM0/7

FSCG delivere d

by the circuit

FSCV* de livere d

by the circuit

The four Multiplex Configura tion Registers are a t zero (no de lay).

Figure 27 : Clocks received and delivered by the Multi-HDLC

Symbol

Parameter

Min.

Typ.

Max.

Unit

Clock Period if 4096kHz

Clock Period if 8192kHz

239

120

244

122

249

125

Delay between Clock A and Clock B

- 60

+60

Set up time Frame A (or B)/CLOCK A (or B)

t1-10

t4GCI

Hold time Frame A (or B)/CLOCK A (or B)

t1-10

125000 - (t1 - 10)

Clock ratio t5h/t5l

100

125

STLC5464

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