STLC5466 datasheet(36/130 Pages) STMICROELECTRONICS

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STLC5466

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SAV

: Pseudo Random Sequence analyser Validated

SAV = 1, PRS analyser is validated.

SAV = 0, PRS analyser is reset.

SGC

: Pseudo Random Sequence Generator Corrupted

When SGC bit goes from 0 to 1, one bit of sequence transmitted is corrupted.

When the corrupted bit has been transmitted, SGC bit goes from 1 to 0 automatically.

: MESSAGE ENABLE

ME = 1 The contents of Connection Memory is output on DOUT0/7 continuously.

ME = 0 The contents of Connection Memory acts as an address for the Data Memory.

AISD

Alarm Indication Signal Detection.

AISD=1, the Alarm Indication Signal detection is validated.

Sixteen independent detections are performed for sixteen hyperchannels. The contents of any

input hyperchannel (B1, B2) switched (in transparent mode or not) on GCI channels is ana-

lysed independently.

For each GCI channel, the 16 bits of B1and B2 channels are checked together; when all “one”

has been detected during 30 milliseconds, a status is stored in the Command/ Indicate inter-

rupt queue and an interrupt is generated if not masked (like the reception of primitive from GCI

multiplexes).

AISD=0, the Alarm Indication Signal detection for 16 hyperchannels is not validated.

DR04

: Data Rate of TDM0 is at 4Mb/s (Case: M1=M0=0).

DR04 = 1, the signal received from DIN0 pin and the signal delivered by Dout0 pin are at 4Mb/

s. DIN1 pin and DOUT1 pin are ignored.

The Time Division Multiplex 0 is constituted by 64 contiguous timeslots numbered from 0 to 63.

DR04 = 0, the signals received from DIN0/1 pins and the signals delivered by Dout0/1 pins are

at 2Mb/s.

DR24

: Data Rate of TDM2 is at 4Mb/s (Case: M1=M0=0).

DR24 = 1, the signal received from DIN2 pin and the signal delivered by Dout2 pin are at 4Mb/

s. DIN3 pin and DOUT3 pin are ignored.

The Time Division Multiplex 2 is constituted by contiguous 64 timeslots numbered from 0 to 63.

DR24 = 0, the signals received from DIN2/3 pins and the signals delivered by Dout2/3 pins are

at 2Mb/s.

DR44

: Data Rate of TDM4 is at 4Mb/s (Case: M1=M0=0).

DR44 = 1, the signal received from DIN4 pin and the signal delivered by Dout4 pin are at 4Mb/

s. DIN5 pin and DOUT5 pin are ignored.

TDM4/5 cannot be GCI multiplexes.

The Time Division Multiplex 4 is constituted by 64 contiguous timeslots numbered from 0 to 63.

DR44 = 0, the signals received from DIN4/5 pins and the signals delivered by Dout4/5 pins are

at 2Mb/s.

DR64

: Data Rate of TDM6 is at 4Mb/s (Case: M1=M0=0).

DR64 = 1, the signal received from DIN6 pin and the signal delivered by Dout6 pin are at 4Mb/

s. DIN7 pin and DOUT7 pin are ignored.

The Switching Matrix cannot be used to switch the channels to/from the HDLC controllers but

the RX HDLC controller can be connected to DIN8 and the TX HDLC controller can be con-

nected to CB pin.

The Time Division Multiplex 6 is constituted by 64 contiguous timeslots numbered from0 to 63.

DR64 = 0, the signals received from DIN6/7 pins and the signals delivered by

Dout6/7 pins are at 2M b/s.

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