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L5994 - L5994A

Input Capacitors

A pulsed current (with zero average value) flows through the input capacitor of a buck converter. The AC com-

ponent of this current is quite high and dissipates a considerable amount of power on the ESR of the capacitor:

It is easy to find that PCIN has a maximum equal to IOUT/2 (@ VIN=2×VOUT, that is, 50% duty cycle). The

input capacitor of each section, therefore, should be selected for a RMS ripple current rating as high as half the

respective maximum output current. The capacitance value is not very important but in reality a minimum value

must be ensured for stability reasons. In fact, switching regulators exhibit a negative input impedance that, at

low frequencies, is:

the bandwidth of the regulator control loop, there is the possibility for oscillations. To ensure stability, the follow-

ing condition must be satisfied:

input capacitor itself.The use of high performance electrolytic capacitors is recommended. If a higher cost is of

no concern, OS-CON capacitors are an excellent choice because they offer the smallest size for a given ESR

or current rating. Tantalum capacitors do not tolerate pulsed current, so their use is not advisable.

Output Capacitors

The output capacitor selection is based on the output voltage ripple requirements. This ripple is related to the

current ripple through the inductor and is almost entirely due to the ESR of the output capacitor. Therefore, the

goal is to achieve an ESR lower than a certain value, regardless of the actual capacitance value.

The maximum current ripple of the +3.3V section is:

considering the values obtained in the paragraph "+3.3V inductor". As for the +5.1V, the maximum ripple is giv-

en by:

Anyhow, the maximum ESR will be:

where the subscript x refers to either section.

In pulse-skipping operation, the capacitive component of the output ripple is comparable to the resistive one,

Pc

IN

ESR I

OUT

2

V

OUT

V

IN

V

OU T

–

()

⋅

V

IN

2

-------------------------------------------------------

⋅⋅

=

Z

IN D C

()

V

IN

2

V

OUT

I

OUT

⋅

--------------------------------

=

C

IN

L

EQ

ESR

IN

Z

IN D C

()

⋅

-----------------------------------------------

»

I

L5

∆η I

OUT 12

V

IN

V

IN

5.1

–

-----------------------

3

4

---

5.1

V

IN

5.1

–

()

⋅

f

SW

L

3P

V

IN

⋅⋅

-----------------------------------------

⋅

+

⋅⋅

=

ESR

X

V

RPKX

I

LX

∆

------------------

≤