L6732_08 datasheet(24/37 Pages) STMICROELECTRONICS

24 / 37 page

Application details

L6732

24/37

Where D is the duty cycle. The equation reaches its maximum value, IOUT /2 with D = 0.5.

The losses in worst case are:

Equation 12

6.4

Compensation network

The loop is based on a voltage mode control (Figure 18.). The output voltage is regulated to

the internal/external reference voltage and scaled by the external resistor divider. The error

amplifier output VCOMP is then compared with the oscillator triangular wave to provide a

pulse-width modulated (PWM) with an amplitude of VIN at the PHASE node. This waveform

is filtered by the output filter. The modulator transfer function is the small signal transfer

function of VOUT/VCOMP. This function has a double pole at frequency FLC depending on the

L-COUT resonance and a zero at FESR depending on the output capacitor's ESR. The DC

Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator

voltage: VOSC.

The compensation network consists in the internal error amplifier, the impedance networks

ZIN (R3, R4 and C20) and ZFB (R5, C18 and C19). The compensation network has to

provide a closed loop transfer function with the highest 0dB crossing frequency to have

fastest transient response (but always lower than fsw/10) and the highest gain in DC

conditions to minimize the load regulation error. A stable control loop has a gain crossing the

0dB axis with -20dB/decade slope and a phase margin greater than 45 °. To locate poles

and zeroes of the compensation networks, the following suggestions may be used:

●

Modulator singularity frequencies:

Equation 13

)

(

Iout

ESR

⋅

Figure 18.

Compensation network

Cout

⋅

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