M74HC298

2/11

INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

TRUTH TABLE

X : Don’t Care

a1, a2, ETC. : The level of steady state input at a1, a2, etc.

QA0, QB0, ETC. : The level of QA, QB, ETC entered on the most recent negative transition of the clock input.

LOGIC DIAGRAM

This logic diagram has not be used to estimate propagation delays

PIN No

SYMBOL

NAME AND FUNCTION

1, 2, 5, 6

A2, B2, C2,

D2

Word 2 Data Inputs

3, 4, 7, 9

A1, B1, C1,

D1

Word 1 Data Inputs

12 to 15

QA to QD

Outputs

10

WORD

SELECT

Word Select Input

11

CLOCK

Clock Input (LOW to

HIGH, Edge-triggered)

8

GND

Ground (0V)

16

Positive Supply Voltage

INPUTS

OUTPUTS

WORD SELECT

CLOCK

QA

QB

QC

QD

L

a1

b1c1d1

H

a2

b2c2d2

X

QA0

QB0

QC0

QD0