V62C31864 datasheet(2/12 Pages) MOSEL

2 / 12 page

V62C31864 Rev. 1.6 August 1998

MOSEL VITELIC

V62C31864

Pin Descriptions

A0–A12

Address Inputs

These 13 address inputs select one of the 8,192 x 8

bit segments in the RAM.

CE1, CE2 Chip Enable Inputs

CE1 is active LOW and CE2 is active HIGH. Both

chip enables must be active to read from or write to

the device. If either chip enable is not active, the

device is deselected and is in a standby power

mode. The I/O pins will be in the high-impedance

state when deselected.

Output Enable Input

The Output Enable input is active LOW. When OE

is LOW with CE1 LOW, CE2 HIGH, and WE HIGH,

data of the selected memory location will be

available on the I/O pins. When OE is HIGH, the I/O

pins will be in the high impedance state.

Write Enable Input

An active LOW input, WE input controls read and

write operations. When CE1 and WE inputs are

both LOW with CE2 HIGH, the data present on the

I/O pins will be written into the selected memory

location.

I/O0–I/O7 Data Input and Data Output Ports

These 8 bidirectional ports are used to read data

from and write data into the RAM.

VCC

Power Supply

GND

Ground

Pin Configurations (Top View)

28-Pin SOP

28-Pin TSOP (Standard)

VCC

A11

A10

I/O0

I/O1

I/O2

GND

I/O7

I/O6

I/O5

I/O4

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CE2

A12

I/O3

CE1

A11

CE2

VCC

A12

A10

CE1

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

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