STV7733

Power output stage

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Power output stage

The power output stage is defined by a set of three switches that can select three different

the output stage in a high impedance (Hi-Z) mode.

Depending on the configuration of logic inputs AOC1 and AOC2, the power output stage is

configured in either a “data through” mode or a “simultaneous” mode. In the “data through”

mode (for AOC1 = AOC2 = “L”), the power output stage converts the 2-bit encoded data that

was loaded into the latch stage for each column into a high-voltage level that appears on the

output pin. When AOC1 and AOC2 are not both “L”, the power outputs can all operate

below in Table 3.

Table 3.

Power output truth table

DBn[1]

DBn[2]

POE

AOC1

AOC2

OUTn

Comment

X

X

L

X

X

All Hi-Z

(1)

1.

With input POE = “L”, all power outputs are not active, that is, they are all in Hi-Z.

L

L

H

L

L

Hi-Z

(2)

2.

Data through mode: each power output depends on the DBn[1:2] value at the falling edge of input /DL.

H

L

H

L

L

(2)

H

H

H

L

L

(2)

L

H

H

L

L

(2)

X

X

H

H

L

(3)

3.

Output simultaneous mode: all power outputs depend on the “H”/”L” input values for AOC1 and AOC2.

X

X

H

L

H

(3)

X

X

H

H

H

(3)