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V62C5181024 Datenblatt(PDF) 1 Page - Mosel Vitelic, Corp |
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V62C5181024 Datenblatt(HTML) 1 Page - Mosel Vitelic, Corp |
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1 / 12 page ![]() MOSEL VITELIC 1 V62C5181024 128K X 8 STATIC RAM PRELIMINARY V62C5181024 Rev. 2.2 February 2000 Features s High-speed: 35, 70 ns s Ultra low DC operating current of 5mA (max.) TTL Standby: 5 mA (Max.) CMOS Standby: 60 µA (Max.) s Fully static operation s All inputs and outputs directly compatible s Three state outputs s Ultra low data retention current (VCC = 2V) s Single 5V ± 10% Power Supply s Packages – 32-pin TSOP (Standard) – 32-pin 600 mil PDIP – 32-pin 440 mil SOP (525 mil pin-to-pin) Description The V62C5181024 is a 1,048,576-bit static random-access memory organized as 131,072 words by 8 bits. It is built with MOSEL VITELIC’s high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Device Usage Chart Operating Temperature Range Package Outline Access Time (ns) Power Temperature Mark TW P 35 70 L LL 0 °C to 70 °C ••••• • • Blank –40 °C to +85°C ••••• • • I Functional Block Diagram Row Decoder 1024 x 1024 Memory Array Input Data Circuit Column I/O Column Decoder Control Circuit VCC GND A0 5181024 01 A9 I/O0 I/O7 CE2 OE WE CE1 A10 A16 |
Ähnliche Teilenummer - V62C5181024 |
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Ähnliche Beschreibung - V62C5181024 |
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