M38049FFHKP datasheet(14/116 Pages) RENESAS

14 / 116 page

Rev.1.01

Jan 25, 2005

page 14 of 114

REJ03B0131-0101Z

3804 Group (Spec. H)

I/O PORTS

The I/O ports have direction registers which determine the input/

output direction of each individual pin. Each bit in a direction reg-

ister corresponds to one pin, and each pin can be set to be input

port or output port.

When “0” is written to the bit corresponding to a pin, that pin be-

P00/AN8–P07/AN15

P10/INT41

P11/INT01

P12–P17

P20/LED0–

P27/LED7

P30/DA1

P31/DA2

P32/SDA

P33/SCL

P34/RxD3

P35/TxD3

P36/SCLK3

P37/SRDY3

P40/INT40/XCIN

P41/INT00/XCOUT

P42/INT1

P43/INT2

P44/RxD1

P45/TxD1

P46/SCLK1

P47/SRDY1/CNTR2

Name

I/O Structure

CMOS compatible input level

CMOS 3-state output

Non-Port Function

Ref.No.

Table 5 I/O port function

Related SFRs

Port P0

Port P1

Port P3

(1)

(2)

Port P2

A/D converter input

External interrupt input

D/A converter output

AD/DA control register

Interrupt edge selection

AD/DA control register

(3)

(4)

(5)

CMOS compatible input level

CMOS 3-state output

CMOS compatible input level

N-channel open-drain output

CMOS/SMBUS input level (when

selecting I2C-BUS interface function)

CMOS compatible input level

CMOS 3-state output

Port P4

Serial I/O3 function I/O

Serial I/O3 control

UART3 control register

(6)

(7)

(8)

(9)

External interrupt input

Sub-clock generating

circuit

External interrupt input

Serial I/O1 function I/O

Interrupt edge selection

CPU mode register

Interrupt edge selection

Serial I/O1 control

UART1 control register

(10)

(11)

(2)

(6)

(7)

(8)

(12)

Serial I/O1 function I/O

Timer Z function I/O

Serial I/O1 control

Timer Z mode register

Serial I/O2 control

Serial I/O2 function I/O

Port P5

Port P6

(13)

(14)

(15)

(16)

(17)

(18)

(2)

(1)

Timer X, Y function I/O

PWM output

External interrupt input

A/D converter input

Timer XY mode register

PWM control register

Interrupt edge selection

AD/DA control register

Notes 1: Refer to the applicable sections how to use double-function ports as function I/O ports.

2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.

When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.

comes an input pin. When “1” is written to that bit, that pin be-

comes an output pin.

If data is read from a pin which is set to output, the value of the

port output latch is read, not the value of the pin itself. Pins set to

input are floating. If a pin set to input is written to, only the port

output latch is written to and the pin remains floating.

P50/SIN2

P51/SOUT2

P52/SCLK2

P53/SRDY2

P54/CNTR0

P55/CNTR1

P56/PWM

P57/INT3

P60/AN0–P67/AN7

CMOS compatible input level

CMOS 3-state output

CMOS compatible input level

CMOS 3-state output

CMOS compatible input level

CMOS 3-state output

I2C-BUS interface func-

tion I/O

I2C control register

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