M38045F1HKP datasheet(98/116 Pages) RENESAS

98 / 116 page

Rev.1.01

Jan 25, 2005

page 98 of 114

REJ03B0131-0101Z

3804 Group (Spec. H)

NOTES ON PROGRAMMING

Processor Status Register

The contents of the processor status register (PS) after a reset are

undefined, except for the interrupt disable flag (I) which is “1.” Af-

ter a reset, initialize flags which affect program execution. In

particular, it is essential to initialize the index X mode (T) and the

decimal mode (D) flags because of their effect on calculations.

Interrupts

The contents of the interrupt request bits do not change immedi-

ately after they have been written. After writing to an interrupt

request register, execute at least one instruction before perform-

ing a BBC or BBS instruction.

Decimal Calculations

• To calculate in decimal notation, set the decimal mode flag (D)

to “1”, then execute an ADC or SBC instruction. After executing

an ADC or SBC instruction, execute at least one instruction be-

fore executing a SEC, CLC, or CLD instruction.

• In decimal mode, the values of the negative (N), overflow (V),

and zero (Z) flags are invalid.

Timers

If a value n (between 0 and 255) is written to a timer latch, the fre-

quency division ratio is 1/(n+1).

Multiplication and Division Instructions

• The index X mode (T) and the decimal mode (D) flags do not af-

fect the MUL and DIV instruction.

• The execution of these instructions does not change the con-

tents of the processor status register.

Ports

The contents of the port direction registers cannot be read. The

following cannot be used:

• The data transfer instruction (LDA, etc.)

• The operation instruction when the index X mode flag (T) is “1”

• The instruction with the addressing mode which uses the value

of a direction register as an index

• The bit-test instruction (BBC or BBS, etc.) to a direction register

• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to

a direction register.

Use instructions such as LDM and STA, etc., to set the port direc-

tion registers.

Serial Interface

In clock synchronous serial I/O, if the receive side is using an ex-

ternal clock and it is to output the SRDY signal, set the transmit

enable bit, the receive enable bit, and the SRDY output enable bit

to “1.”

Serial I/O continues to output the final bit from the TXD pin after

transmission is completed. SOUT2 pin for serial I/O2 goes to high

impedance after transfer is completed.

When in serial I/Os 1 and 3 (clock-synchronous mode) or in serial

I/O2, an external clock is used as synchronous clock, write trans-

mission data to the transmit buffer register or serial I/O2 register,

during transfer clock is “H.”

A/D Converter

The comparator uses capacitive coupling amplifier whose charge

will be lost if the clock frequency is too low.

Therefore, make sure that f(XIN) is at least on 500 kHz during an

A/D conversion.

Do not execute the STP instruction during an A/D conversion.

D/A Converter

The accuracy of the D/A converter becomes rapidly poor under

the VCC = 4.0 V or less condition; a supply voltage of VCC

≥ 4.0 V

is recommended. When a D/A converter is not used, set all values

of D/Ai conversion registers (i=1, 2) to “0016.”

Instruction Execution Time

The instruction execution time is obtained by multiplying the pe-

riod of the internal clock

φ by the number of cycles needed to

execute an instruction.

The number of cycles required to execute an instruction is shown

in the list of machine instructions.

The period of the internal clock

φ is double of the XIN period in

high-speed mode.

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