M38043F7HKP datasheet(34/116 Pages) RENESAS

34 / 116 page

Rev.1.01

Jan 25, 2005

page 34 of 114

REJ03B0131-0101Z

3804 Group (Spec. H)

Fig. 24 Block diagram of timer Z

“1”

“0”

P42/INT1

P47/CNTR2

“0”

“1”

“001”

“100”

“101”

f(XCIN)

XIN

XCIN

Output level latch

Programmable one-shot

generating mode

Programmable one-shot

generating circuit

CNTR2 active edge

switch bit

Programmable one-shot

generating mode

Data bus

To timer Z interrupt

request bit

To CNTR2 interrupt

request bit

To INT1 interrupt

request bit

Programmable waveform

generating mode

Pulse output mode

CNTR2 active edge switch bit

Pulse output mode

Timer Z low-order latch

Timer Z low-order

Timer Z high-order latch

Timer Z high-order

Timer Z operating

mode bits

Port P47

direction register

Port P47

latch

Pulse period measurement mode

Pulse width measurement mode

Edge detection circuit

Timer Z count stop bit

Count source

selection bit

(1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024)

Divider

CNTR2 active edge

switch bit

“1”

“0”

“1”

Timer/Event

counter mode

switch bit

M38043F7HKP Datenblatt(PDF) 34 Page - Renesas Technology Corp

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