7480 datasheet(59/98 Pages) RENESAS

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MITSUBISHI MICROCOMPUTERS

7480/7481 GROUP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PRELIMINAR

Notice:

This

is not

a final

specification.

Some

parametric

limits

are

subject

to change.

Table 13. Recommended operating conditions (cont.)

Symbol

Parameter

Standard values

Min.

Typ.

Max.

Unit

250

500

2.2VCC –2

f(CNTR)

f(SCLK)

f(XIN)

f(XIN) = 4 MHz

f(XIN) = 8 MHz

f(XIN) = 4 MHz

f(XIN) = 8 MHz

f(XIN) = 4 MHz

f(XIN) = 8 MHz

VCC = 2.7 to 4.5 V

VCC = 4.5 to 5.5 V

MHz

kHz

MHz

Timer input frequency CNTR0 (P40),

CNTR1 (P41) (Note 3)

Clock input oscillation frequency (Note 3)

Serial I/O clock input

frequency SCLK (P16)

(Note 3)

Clock synchronous

serial I/O mode

UART mode

Notes 1 : –40 to 85 °C for extended operating temperature range version.

2 : The average output currents IOH(avg) and IOL(avg) are the average values during 100 ms.

3 : The clock input oscillation frequency is at 50 % duty ratio.

4 : When applying a voltage through a resistor as shown in the figure 55, VI > VCC may be accepted if the current is 1 mA or less.

Fig. 55 Notes on use of ports P4 and P5

Notes on Clamp Diode (7481 Group)

(1) Total input current

The current of ports P4 and P5 through the clamp diode can

be drawn up to 1.0 mA per port. When a current that cannot be

consumed by microcomputer is sent flow to the clamp diode,

this may raise the power source pin voltage of the microcom-

puter.

The system power circuit must be designed so that the power

source voltage of the microcomputer may be stabilized within

the standard values.

(2) Maximum input voltage

If the input voltage of a signal connected to ports P4 and P5 is

beyond VCC + 0.3 V, the input waveform should have a delay

exceeding 2

µs/V from the moment that this waveform goes

over the voltage.

For using a CR circuit for delay, calculate a proper delay value

by the following expression:

where VIN = Maximum input voltage amplitude margin and

t = C ! R.

=≥ 2 ! 10–6 (s/V)

0.6 ! VIN

Port P4, P5

The clamp diode of the 7480/7481 group is designed for a level

shift of DC signal unlike ordinary switching diodes. Do not apply

sudden stress, such as rush current, directly to the diode.

Notes on Countermeasures for Noise and

Latch-up (7481 Group)

(1) Connect a bypass capacitor (0.1

µF) across the VCC pin and

the VSS pin with the shortest possible wiring, using a relatively

thick wire.

(2) Connect a bypass capacitor (0.01

µF) across the VREF pin and

the VSS pin with the shortest possible wiring, using a relatively

thick wire.

(3) In the oscillation circuit, connect across the XIN and XOUT pins

with the shortest possible wiring. Connect the GND and VSS

pins of the oscillation circuit with the shortest possible wiring,

using a relatively thick wire.

(4) In the case of the P33/VPP pin of the built-in programmable

ROM version, connect an approximately 5 k

Ω resistor to the

P33/VPP pin the shortest possible in series.

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