HD74AC164/HD74ACT164

Rev.2.00, Jul.16.2004, page 2 of 8

Logic Symbol

A

B

CP

Pin Names

A, B

Data Inputs

CP

Clock Pulse Input (Active Rising Edge)

MR

Master Reset Input (Active Low)

Q

Outputs

Functional Description

The HD74AC164/HD74ACT164 is an edge-triggered 8-bit shift register with serial data entry and an output from each

of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an

active High Enable for data entry through the other inputs. An unused input must be tied High.

Each Low-to-High transition on the Clock (CP) input shifts data one place to the right and enters into Q

AND of the two data inputs (A•B) that existed before the rising clock edge. A Low level on the Master Reset (

MR)

input overrides all other inputs and clears the register asynchronously, forcing all Q outputs Low.

Mode Select Table

Inputs

Outputs

Operating Mode

MR

MR

MR

MR

AB

Q

0

Q

Reset (Clear)

L

X

X

L

L to L

Shift

H

LLL

q

HL

HL

q

HHL

L

q

HHHH

q

H :

High Voltage Level

L

:

Low Voltage Level

X :

Immaterial

q

n

:

Lower case letters indicate the state of the referenced input or output one setup time prior to the Low-to-High

clock transition.

Logic Diagram

A

B

CP

MR

D

QD

QD

QD

QD

QD

QD

QD

Q

Please note that this diagram is provided only for the understanding of logic operations and should not be

used to estimate propagation delays.