SH7672 datasheet(86/1292 Pages) RENESAS

86 / 1292 page

Section 2 CPU

Rev. 1.00 Nov. 14, 2007 Page 60 of 1262

REJ09B0437-0100

Compatibility

Instruction

Instruction Code

Operation

Execu-

tion

Cycles

T Bit

SH2,

SH2E SH4

SH-2A

CLIPS.B

0100nnnn10010001

When Rn > (H'0000007F),

(H'0000007F)

→ Rn, 1 → CS

when Rn < (H'FFFFFF80),

(H'FFFFFF80)

→ Rn, 1 → CS



Yes

CLIPS.W

0100nnnn10010101

When Rn > (H'00007FFF),

(H'00007FFF)

→ Rn, 1 → CS

When Rn < (H'FFFF8000),

(H'FFFF8000)

→ Rn, 1 → CS



Yes

CLIPU.B

0100nnnn10000001

When Rn > (H'000000FF),

(H'000000FF)

→ Rn, 1 → CS



Yes

CLIPU.W

0100nnnn10000101

When Rn > (H'0000FFFF),

(H'0000FFFF)

→ Rn, 1 → CS



Yes

DIV1

Rm,Rn

0011nnnnmmmm0100

1-step division (Rn

÷ Rm)

Calcu-

lation

result

Yes

DIV0S

Rm,Rn

0010nnnnmmmm0111

MSB of Rn

→ Q,

MSB of Rm

→ M, M ^ Q → T

Calcu-

lation

result

Yes

DIV0U

0000000000011001

→ M/Q/T

Yes

DIVS

R0,Rn

0100nnnn10010100

Signed operation of Rn

÷ R0

→ Rn 32 ÷ 32 → 32 bits



Yes

DIVU

R0,Rn

0100nnnn10000100

Unsigned operation of Rn

÷ R0

→ Rn 32 ÷ 32 → 32 bits



Yes

DMULS.L Rm,Rn

0011nnnnmmmm1101

Signed operation of Rn

× Rm

→ MACH, MACL

× 32 → 64 bits



Yes

DMULU.L Rm,Rn

0011nnnnmmmm0101

Unsigned operation of Rn

→ MACH, MACL

× 32 → 64 bits



Yes

0100nnnn00010000

– 1

→ Rn

When Rn is 0, 1

→ T

When Rn is not 0, 0

→ T

Compa-

rison

result

Yes

EXTS.B

Rm,Rn

0110nnnnmmmm1110

Byte in Rm is

sign-extended

→ Rn



Yes

EXTS.W

Rm,Rn

0110nnnnmmmm1111

Word in Rm is

sign-extended

→ Rn



Yes

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