HD64F2149YV datasheet(345/1075 Pages) RENESAS

345 / 1075 page

Section 11 16-Bit Free-Running Timer

Rev. 3.00 Jan 18, 2006 page 317 of 1044

REJ09B0280-0300

Bit 7

ICIAE

Description

Input capture interrupt request A (ICIA) is disabled

(Initial value)

Input capture interrupt request A (ICIA) is enabled

Bit 6—Input Capture Interrupt B Enable (ICIBE): Selects whether to request input capture

interrupt B (ICIB) when input capture flag B (ICFB) in TCSR is set to 1.

Bit 6

ICIBE

Description

Input capture interrupt request B (ICIB) is disabled

(Initial value)

Input capture interrupt request B (ICIB) is enabled

Bit 5—Input Capture Interrupt C Enable (ICICE): Selects whether to request input capture

interrupt C (ICIC) when input capture flag C (ICFC) in TCSR is set to 1.

Bit 5

ICICE

Description

Input capture interrupt request C (ICIC) is disabled

(Initial value)

Input capture interrupt request C (ICIC) is enabled

Bit 4—Input Capture Interrupt D Enable (ICIDE): Selects whether to request input capture

interrupt D (ICID) when input capture flag D (ICFD) in TCSR is set to 1.

Bit 4

ICIDE

Description

Input capture interrupt request D (ICID) is disabled

(Initial value)

Input capture interrupt request D (ICID) is enabled

Bit 3—Output Compare Interrupt A Enable (OCIAE): Selects whether to request output

compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1.

Bit 3

OCIAE

Description

Output compare interrupt request A (OCIA) is disabled

(Initial value)

Output compare interrupt request A (OCIA) is enabled

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