H8SXSLASH1663 datasheet(332/1158 Pages) RENESAS

Teilenummer	H8SX/1663

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

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Hersteller	RENESAS [Renesas Technology Corp]

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 280 of 1102

REJ09B0294-0100

Some DRAMs with the self-refresh mode have a given time between cancellation of the self-

refresh mode and the subsequent command issued cycle. From one to seven of precharge cycles

immediately after cancellation of the self-refresh mode can be inserted. Normal precharge is also

performed according to bits TPC1 and TPC0 in DRACCR. Set the precharge time including the

normal precharge so that the precharge time immediately after a self-refresh cycle is optimal.

Figure 6.80 shows a timing example when one precharge cycle is added.

Address bus

Software

standby

SDRAM space write

Data bus

Precharge-sel

RAS

CAS

PALL

ACTV

WRITE

NOP

DQMUU, DQMUL

DQMLU, DQMLL

CKE

RD/

Figure 6.80 Timing Example when 1 Precharge Cycle Added

(TPC2 to TPC0 = H'1, TPC1 = 0, TPC0 = 0)

H8SX/1663 Datenblatt(PDF) 332 Page - Renesas Technology Corp