H8SXSLASH1663 datasheet(45/1158 Pages) RENESAS

45 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xlv of lii

Tables

Section 1 Overview

Table 1.1

Pin Configuration in Each Operating Mode.............................................................. 4

Table 1.2

Pin Functions ............................................................................................................ 9

Section 2 CPU

Table 2.1

Instruction Classification ........................................................................................ 38

Table 2.2

Combinations of Instructions and Addressing Modes (1)....................................... 40

Table 2.2

Combinations of Instructions and Addressing Modes (2)....................................... 43

Table 2.3

Operation Notation ................................................................................................. 44

Table 2.4

Data Transfer Instructions....................................................................................... 45

Table 2.5

Block Transfer Instructions..................................................................................... 46

Table 2.6

Arithmetic Operation Instructions .......................................................................... 47

Table 2.7

Logic Operation Instructions .................................................................................. 49

Table 2.8

Shift Operation Instructions .................................................................................... 49

Table 2.9

Bit Manipulation Instructions ................................................................................. 50

Table 2.10

Branch Instructions ................................................................................................. 52

Table 2.11

System Control Instructions.................................................................................... 53

Table 2.12

Addressing Modes .................................................................................................. 55

Table 2.13

Absolute Address Access Ranges ........................................................................... 58

Table 2.14

Effective Address Calculation for Transfer and Operation Instructions ................. 62

Table 2.15

Effective Address Calculation for Branch Instructions........................................... 63

Section 3 MCU Operating Modes

Table 3.1

MCU Operating Mode Settings .............................................................................. 65

Table 3.2

SDRAM Interface Selection for MCU Operating Mode......................................... 65

Table 3.3

Settings of Bits MDS3 to MDS0............................................................................. 67

Table 3.4

Pin Functions in Each Operating Mode (Advanced Mode) .................................... 72

Section 4 Exception Handling

Table 4.1

Exception Types and Priority.................................................................................. 77

Table 4.2

Exception Handling Vector Table........................................................................... 78

Table 4.3

Calculation Method of Exception Handling Vector Table Address........................ 80

Table 4.4

Status of CCR and EXR after Trace Exception Handling....................................... 83

Table 4.5

Bus Cycle and Address Error.................................................................................. 84

Table 4.6

Status of CCR and EXR after Address Error Exception Handling ......................... 85

Table 4.7

Interrupt Sources..................................................................................................... 86

Table 4.8

Status of CCR and EXR after Trap Instruction Exception Handling...................... 88

Table 4.9

Status of CCR and EXR after Sleep Instruction Exception Handling..................... 89

Table 4.10

Status of CCR and EXR after Illegal Instruction Exception Handling ................... 90

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