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H8SX/1663 Datenblatt(PDF) 337 Page - Renesas Technology Corp

Teilenummer H8SX/1663
Bauteilbeschribung  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663 Datenblatt(HTML) 337 Page - Renesas Technology Corp

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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 285 of 1102
REJ09B0294-0100
(2) When DDS = 0
Single address transfer by the DMAC takes place as a full access (normal access) to the SDRAM
space. The
DACK signal is asserted within the Tr cycle and the BS signal is also asserted in the Tr
cycle.
When the SDRAM space is accessed with other than the single address transfer by the DMAC, a
fast-page access is available.
Figures 6.84 and 6.85 show an output timing example of the
DACK signal when DDS = 0.
T
p
T
r
T
c1
T
c2
Address bus
Row address
Column address
SD
φ
CS
Precharge-sel
RAS
CAS
WE
CKE
PALL
ACTV
WRIT
NOP
DQMLU
DQMLL
D7 to D0
BS
RD/
WR
D15 to D8
Row
address
High
DACK
Figure 6.84 Output Timing Example of
DACK when DDS = 0 (Write)



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