H8SXSLASH1663 datasheet(383/1158 Pages) RENESAS

383 / 1158 page

Section 7 DMA Controller (DMAC)

Rev.1.00 Jun. 07, 2006 Page 331 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

ERRF

R/(W)* System Error Flag

Indicates that an address error or an NMI interrupt has

been generated. This bit is available only in DMDR_0.

Setting this bit to 1 prohibits writing to the DTE bit for all

the channels. This bit is reserved in DMDR_1 to

DMDR_3. It is always read as 0 and cannot be modified.

0: An address error or an NMI interrupt has not been

generated

1: An address error or an NMI interrupt has been

generated

[Clearing condition]

• When clearing to 0 after reading ERRF = 1

[Setting condition]

• When an address error or an NMI interrupt has been

generated

However, when an address error or an NMI interrupt has

been generated in DMAC module stop mode, this bit is

not set to 1.



Reserved

This bit is always read as 0 and cannot be modified.

ESIF

R/(W)* Transfer Escape Interrupt Flag

Indicates that a transfer escape end interrupt has been

requested. A transfer escape end means that a transfer

is terminated before the transfer counter reaches 0.

0: A transfer escape end interrupt has not been

requested

1: A transfer escape end interrupt has been requested

[Clearing conditions]

• When setting the DTE bit to 1

• When clearing to 0 before reading ESIF = 1

[Setting conditions]

• When a transfer size error interrupt is requested

• When a repeat size end interrupt is requested

• When a transfer end interrupt by an extended repeat

area overflow is requested

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