H8SXSLASH1663 datasheet(419/1158 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev.1.00 Jun. 07, 2006 Page 367 of 1102

REJ09B0294-0100

(6) ACT Bit in DMDR

The ACT bit in DMDR indicates whether the DMAC is in the idle or active state. When DTE = 0

or DTE = 1 and the DMAC is waiting for a transfer request, the ACT bit is 0. Otherwise (the

DMAC is in the active state), the ACT bit is 1. When individual transfers are stopped by writing 0

and the transfer is not completed, the ACT bit retains 1.

In block transfer mode, even if individual transfers are stopped by writing 0 to the DTE bit, the 1-

block size of transfers is not stopped. The ACT bit retains 1 from writing 0 to the DTE bit to

completion of a 1-block size transfer.

In burst mode, up to three times of DMA transfer are performed from the cycle in which the DTE

bit is written to 0. The ACT bit retains 1 from writing 0 to the DTE bit to completion of DMA

transfer.

(7) ERRF Bit in DMDR

When an address error or an NMI interrupt occur, the DMAC clears the DTE bits for all the

channels to stop a transfer. In addition, it sets the ERRF bit in DMDR_0 to 1 to indicate that an

address error or an NMI interrupt has occurred regardless of whether or not the DMAC is in

operation.

(8) ESIF Bit in DMDR

When an interrupt by an transfer size error, a repeat size end, or an extended repeat area overflow

is requested, the ESIF bit in DMDR is set to 1. When both the ESIF and ESIE bits are set to 1, a

transfer escape interrupt is requested to the CPU or DTC.

The ESIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus

cycle of the interrupt source is completed.

The ESIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is

resumed by setting the DTE bit to 1 during interrupt handling.

For details on interrupts, see section 7.8, Interrupt Sources.

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