H8SXSLASH1663 datasheet(434/1158 Pages) RENESAS

434 / 1158 page

Section 7 DMA Controller (DMAC)

Rev.1.00 Jun. 07, 2006 Page 382 of 1102

REJ09B0294-0100

(3) Activation Timing by

DREQ Falling Edge

Figure 7.36 shows an example of single address mode activated by the

DREQ signal falling edge.

The

DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately

after the DTE bit write cycle.

When a low level of the

DREQ signal is detected while a transfer request by the DREQ signal is

enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer

request is cleared and starts detecting a high level of the

DREQ signal for falling edge detection. If

a high level of the

DREQ signal has been detected until completion of the single cycle, receiving

the next transfer request resumes and then a low level of the

DREQ signal is detected. This

operation is repeated until the transfer is completed.

Request

Wait

Request

Min. of 3 cycles

Transfer source/

Transfer destination

Single

Bus

released

Bus

released

Bus

released

DMA single

cycle

DMA single

cycle

DREQ

Address bus

DMA

operation

Channel

[1]

[2]

[3]

[4]

[5]

[6]

[7]

Transfer request

enable resumed

Transfer request

enable resumed

[1]

After DMA transfer request is enabled, a low level of the

DREQ signal is detected at the rising edge of the Bφ signal and a transfer

request is held.

[2][5] The DMAC is activated and the transfer request is cleared.

[3][6] A DMA cycle is started and sampling the

DREQ signal at the rising edge of the Bφ signal is started to detect a high level of the

DREQ signal.

[4][7] When a high level of the

DREQ signal has been detected, transfer enable is resumed after completion of the write cycle.

(A low level of the

DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)

Transfer source/

Transfer destination

Single

DACK

Duration of transfer

request disabled

Duration of transfer

request disabled

Figure 7.36 Example of Transfer in Single Address Mode Activated

DREQ Falling Edge

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