H8SXSLASH1663 datasheet(443/1158 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev.1.00 Jun. 07, 2006 Page 391 of 1102

REJ09B0294-0100

Each interrupt source is specified by the interrupt enable bit in the register for the corresponding

channel. A transfer end interrupt by the transfer counter, a transfer size error interrupt, a repeat

size end interrupt, an interrupt by an extended repeat area overflow on the source address, and an

interrupt by an extended repeat area overflow on the destination address are enabled or disabled by

the DTIE bit in DMDR, the TSEIE bit in DMDR, the RPTIE bit in DACR, SARIE bit in DACR,

and the DARIE bit in DACR, respectively.

A transfer end interrupt by the transfer counter is generated when the DTIF bit in DMDR is set to

1. The DTIF bit is set to 1 when DTCR becomes 0 by a transfer while the DTIE bit in DMDR is

set to 1.

An interrupt other than the transfer end interrupt by the transfer counter is generated when the

ESIF bit in DMDR is set to 1. The ESIF bit is set to 1 when the conditions are satisfied by a

transfer while the enable bit is set to 1.

A transfer size error interrupt is generated when the next transfer cannot be performed because the

DTCR value is less than the data access size, meaning that the data access size of transfers cannot

be performed. In block transfer mode, the block size is compared with the DTCR value for

transfer error decision.

A repeat size end interrupt is generated when the next transfer is requested after completion of the

repeat size of transfers in repeat transfer mode. Even when the repeat area is not specified in the

address register, the transfer can be stopped periodically according to the repeat size. At this time,

when a transfer end interrupt by the transfer counter is generated, the ESIF bit is set to 1.

An interrupt by an extended repeat area overflow on the source and destination addresses is

generated when the address exceeds the extended repeat area (overflow). At this time, when a

transfer end interrupt by the transfer counter, the ESIF bit is set to 1.

Figure 7.39 is a block diagram of interrupts and interrupt flags. To clear an interrupt, clear the

DTIF or ESIF bit in DMDR to 0 in the interrupt handling routine or continue the transfer by

setting the DTE bit in DMDR after setting the register. Figure 7.40 shows procedure to resume the

transfer by clearing a interrupt.

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