H8SXSLASH1663 datasheet(469/1158 Pages) RENESAS

469 / 1158 page

Section 8 Data Transfer Controller (DTC)

Rev.1.00 Jun. 07, 2006 Page 417 of 1102

REJ09B0294-0100

8.5.6

Block Transfer Mode

In block transfer mode, one operation transfers one block of data. Either the transfer source or the

transfer destination is designated as a block area by the DTS bit in MRB.

The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When the transfer of one

block ends, the block size counter (CRAL) and address register (SAR when DTS = 1 or DAR

when DTS = 0) specified as the block area is restored to the initial state. The other address register

is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. When

the specified number of transfers ends, an interrupt is requested to the CPU.

Table 8.8 lists the register function in block transfer mode. Figure 8.9 shows the memory map in

block transfer mode.

Table 8.8

Written Back Value

SAR

Source address

DTS =0: Incremented/decremented/fixed*

DTS = 1: SAR initial value

DAR

Destination address

DTS = 0: DAR initial value

DTS =1: Incremented/decremented/fixed*

CRAH

Block size storage

CRAH

CRAL

Block size counter

CRAH

CRB

Block transfer counter

CRB

− 1

Note:

Transfer information writeback is skipped.

Transfer source data area

Transfer destination data area

(specified as block area)

Block area

DAR

SAR

Transfer

1st block

Nth block

Figure 8.9 Memory Map in Block Transfer Mode

(When Transfer Destination is Specified as Block Area)

H8SX/1663 Datenblatt(PDF) 469 Page - Renesas Technology Corp

H8SX/1663 Datenblatt(HTML) 469 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL