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H8SX/1663 Datenblatt(PDF) 631 Page - Renesas Technology Corp |
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H8SX/1663 Datenblatt(HTML) 631 Page - Renesas Technology Corp |
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631 / 1158 page ![]() Section 10 16-Bit Timer Pulse Unit (TPU) Rev.1.00 Jun. 07, 2006 Page 579 of 1102 REJ09B0294-0100 10.10.9 Conflict between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.51 shows the timing in this case. TCNT P φ Input capture signal Address TGR address Write T 1 T 2 TGR write cycle M M TGR Figure 10.51 Conflict between TGR Write and Input Capture |
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