H8SXSLASH1663 datasheet(823/1158 Pages) RENESAS

823 / 1158 page

Section 16 USB Function Module (USB)

Rev.1.00 Jun. 07, 2006 Page 771 of 1102

REJ09B0294-0100

16.3.20

FIFO Clear Register (FCLR)

FCLR is a register to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the

data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared.

Do not clear a FIFO buffer during transfer.

Bit

Bit Name

Initial Value

R/W



Undefined



EP3 CLR

Undefined

EP1 CLR

Undefined

EP2 CLR

Undefined



Undefined



Undefined



EP0o CLR

Undefined

EP0i CLR

Undefined

Bit

Bit Name

Initial

Value

R/W

Description



Undefined



Reserved

The write value should always be 0.

EP3 CLR

Undefined

EP3 Clear

Writing 1 to this bit initializes the endpoint 3 transmit

FIFO buffer.

EP1 CLR

Undefined

EP1 Clear

Writing 1 to this bit initializes both sides of the

endpoint 1 receive FIFO buffer.

EP2 CLR

Undefined

EP2 Clear

Writing 1 to this bit initializes both sides of the

endpoint 2 transmit FIFO buffer.



Undefined



Reserved

The write value should always be 0.

EP0o CLR

Undefined

EP0o Clear

Writing 1 to this bit initializes the endpoint 0 receive

FIFO buffer.

EP0i CLR

Undefined

EP0i Clear

Writing 1 to this bit initializes the endpoint 0 transmit

FIFO buffer.

H8SX/1663 Datenblatt(PDF) 823 Page - Renesas Technology Corp

H8SX/1663 Datenblatt(HTML) 823 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL